인하대학교 아날로그회로설계 two stage OPamp 설계 (손계산, Hspice코드+결과창, layout)

소개글

two stage OPamp 설계+ 같은 회로에서 output stage가 붙은 형태 설계
회로 두 개에 대한 설계 내용입니다.

1. two stage OPamp 설계
손계산, Hspice코드, 결과창, layout
Hspice로는 operating point, ICMR, Vout swing, Av, fu, phase margin, SR, PSRR+ 를 검증했습니다.

2. output stage가 붙은 형태
손계산, Hspice코드, 결과창
Hspice로 더 많은 사양을 검증했고 방법을 알 수 있는 회로도도 첨부하였습니다.
operating point, ICMR, Vout swing, Av, fu, phase margin, SR, CMRR, PSRR+, PSRR-, Vos

목차

I. TWO STAGE OPAMP DESIGN
1. HAND CALCULATION
2. PRE-SIMULATION
3. HSPICE & H.C 비교
4. LAYOUT

II. TWO STAGE OP AMP+OUTPUT STAGE(class A)
1. 회로도
2. hand calculation
3. Operating point, ICMR, Vout swing code
4. Simulation_operating point
5. Simulation_VOUT SWING, ICMR
6. Frequency response code
7. Simulation_Av, phase margin
8. SR code
9. Simulation_SR
10. CMRR code
11. Simulation_CMRR
12. PSRR+ code
13. Simulation_PSRR+
14. PSRR- code
15. Simulation_PSRR-
16. Vos code
17. Simulation_Vos

본문내용

M11CURRENT200U

*DRIVER(M1 GATE:1, M2 GATE:+ INPUT)
M1 3 7 10 100 PN W=126U L=1U
M2 4 2 10 100 PN W=126U L=1U

*ACTIVE LOAD
M3 3 3 0 0 NN W=32U L=1U
M4 4 3 0 0 NN W=32U L=1U

*BIAS CIRCUIT
M5 10 9 100 100 PN W=160U L=1U
M7 9 9 100 100 PN W=80U L=1U
M9 8 8 0 0 NN W=24U L=1U
RB 9 8 14.5K

*SECOND STAGE
M8 6 4 0 0 NN W=32U L=1U
M6 6 9 100 100 PN W=80U L=1U

*OUTPUTSTAGE
M11 100 6 7 7 NN W=48U L=1U
M10 7 8 0 0 NN W=48U L=1U
CL 7 0 1P

*FREQUENCY COMPENSATION
M12 5 100 4 0 NN W=6U L=1U
CC 5 6 2P

.MODEL NN NMOS(LEVEL=1 VTO=0.5 KP=100U TOX=300E-10 GAMMA=0.3
+LAMBDA=0.01 LD=0.1U PHI=0.7 NSUB=1E16 CGSO=400P CGDO=400P
+ CGBO=600P RSH=20 CJ=2E-4 CJSW=1E-9 MJ=0.5 MJSW=0.5)
.MODEL PN PMOS(LEVEL=1 VTO=-0.5 KP=40U TOX=300E-10 GAMMA=0.3
+LAMBDA=0.01 LD=0.1U PHI=0.7 NSUB=1E16 CGSO=400P CGDO=400P
+ CGBO=600P RSH=20 CJ=2E-4 CJSW=1E-9 MJ=0.5 MJSW=0.5)

*COMMON MODE VOLTAGE
VIN 2 0 DC 1.5V

VDD 100 0 DC 3V
.DC VIN 0 3 0.01
.PROBE I(*)
.OP
.END

참고 자료

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