데이터링크 통신을 위한 PLL 주파수합성기 설계

서지정보

ㆍ발행기관 : 대한안전경영과학회 ㆍ수록지정보 : 대한안전경영과학회지 / 17권 / 3호
ㆍ저자명 : 권상철, 강경식

목차

1. 서 론
2. 관련 연구
2.1 DDS를 이용한 PLL 주파수합성기 모델링
2.2 PLL 주파수합성기 모델 Simulation
2.3 PLL 주파수합성기가 적용 된 데이터링크시스템 블록도
2.4 PLL 주파수합성기 제작 및 측정
3. 결 론
5. References

영어 초록

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

참고 자료

없음