카이스트 전자공학실험3 실험5 A/D Conversion 결과보고서

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카이스트 전자공학실험3 전자디자인랩 오실로스코프만들기 실험 5 결과보고서입니다.

목차

1. 실험 목적
2. Problem Statement
3. Hardware block diagram, 회로도
4. program listing
5. The results and discussion of each experiment
6. 검토사항
7. 참고문헌

본문내용

1. 실험 목적
Embedded board에 증폭된 두 채널의 analog 신호에 대한 A/D conversion 기능을 하는 hardware와 software를 구현하자.
Interface Board에 A/D converter와 supplementary circuit을 solding하고 driver module, application program을 작성하자.

2. Problem Statement
Problem 5 (A/D conversion)
Design and implement a dual-channel 10 M sample/sec 8-bit A/D conversion subsystem for the digital storage oscilloscope, which samples and converts two channel analog signals into digital form. Using a driver module program, the digital data for two channels are stored in the main memory of Embedded Board. Then, using an application program, the data is processed to obtain peak-to-peak and average values for each channel.

Input: Two analog signals and control signals
Channel 1 analog signal amplified by a programmable gain amplifier.
-1 V to 1 V, 0 to 100 KHz.
Channel 2 analog signal (to be amplified by a programmable gain amplifier, but not implemented yet). Assume the range of -1 V to 1 V, 0 to 100 KHz.
500 sampling pulses from the CPLD with period from 100 ns to 1 ms.
(100 ns, 200 ns, 400 ns, 1 us, 2 us, 4 us, 10 us,
20 us, 40 us, 100 us, 200 us, 400 us, 1 ms)
ADC SELECT signals from the EPLD.
A/D conversion
Input voltage: 0 to 2 V.
Sampling rate: 10 M sample/s max for single channel.
10 M sample/s max for each of two channels.
Output: 500 samples of 8-bit data (500 bytes) for each channel.
Storage To be stored in the main memory of embedded board.

참고 자료

유영창 외, “EZ-X5 PXA 255 User's Mannual", 1st edition, J.D&T Co., Ltd., 2003.
AD9281: Dual Channel 8-Bit Resolution CMOS ADC, http://www.analog.com
FIFO, http://en.wikipedia.org/wiki/FIFO
Interrupt, http://en.wikipedia.org/wiki/interrupt
Cypress, “CY7C419/21/25/29/33 256/512/1K/2K/4Kx9 Asynchronous FIFO”, www.cypress.com.