캡스톤 - 2020_capstone_final_초고주파응용회로team11_TFET based SRAM bitcell design_Leejaehyuk

소개글

"캡스톤 - 2020_capstone_final_초고주파응용회로team11_TFET based SRAM bitcell design_Leejaehyuk"에 대한 내용입니다.

목차

I. INTRODUCTION
II. TFET DEVICE AND CHARACTERISTICS
III. OPERATION AND EVALUATION OF SRAM
IV. HYBRID GAA BASED 6T SRAM CELL DESIGN
V. SIMULATION RESULTS AND DISCUSSION
VI. CONCLUSION

본문내용

Abstract— Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. We also investigate and express SNM, which is an evaluation element of the SRAM. And finally, we present hybrid GAA 6T SRAM using TFET and MOSFET together.

Index Terms— HSPICE, SNM(Static Noise Margin), SRAM TFET(Tunnel Based FET), ULP(Ultra Low Power), GAA(Gate all around), Ohmic contact

I. INTRODUCTION
THE Internet of Things (IoT) is going to be a key aspect of future electronic industry. This will put a huge demand on portable or remote devices operated by energy harvesters or batteries. The overall power optimization of the system would largely depend on the performance of static random-access memory(SRAM) due to its wide-scale use as microprocessor caches. Supply voltage scaling has been the most attractive approach until recently to reduce the overall power consumption. However, this leads to a significant increase in delay. Moreover, increased leakage current and reduced ON-current are serious drawbacks at lower Vdd. In fact, the fundamental limit of subthreshold swing is the bottleneck of CMOS for further reducing the leakage.
TFET has emerged as one of the promising candidates for ultralow-power (ULP) applications. This is attributed to its band-to-band tunneling mechanism that defies the SS limit of 60 mV/decade in MOSFET. However, unidirectional current conduction of TFET impacts the robustness of SRAM cells due to conflicting read/write requirements. Also, Low Ion in the conventional TFET Poses challenge for deployment in the mainstream CMOS. Therefore, we will try to design a Hybrid GAA 6T SRAM to improve the performance of the existing 6T SRAM and change the number or thickness of TFET’s device packets. The hybrid GAA device is a circuit in which MOSFET and TFET are connected to each transistor in parallel. The completed SRAM will be measured using Hspice to compare performance with the existing SRAM by measuring RSNM, WSNM and HSNM.

참고 자료

A. Tura and J. Woo, “Performance comparison of silicon steep subthreshold FETs,” IEEE Trans. Electron Devices, vol. 57, no. 6, pp. 1362–1368, Jun. 2010.
A.Mallik and A.Chattopadhyay, “Drain-dependence of tunnel field-effect transistor characteristics: The role of the channel,” IEEE Trans. Electron Devices, vol. 58, no. 12, pp. 4250–4257, Dec. 2011.
S. Ahmad, N. Alam, and M. Hasan, “Robust TFET SRAM cell for ultralow power IoT applications,” AEU Int. J. Electron. Commun., vol. 89, pp. 70–76, 2018. doi: 10.1016/j.aeue.2018.03.029.
Sze, S.M. (1981). Physics of Semiconductor Devices. John Wiley & Sons. ISBN 978-0-471-05661-4. Discussion of theory plus device implications.
UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments HSPICE Tutorial
Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS design considerations,” in
S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3re ed. New York: Wiley-Interscience, 2007
Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, “Tunneling field-effect transistor: Capacitance components and modeling,” IEEE Electron Dev. Lett., vol. 31, no. 7, pp. 752-754, Jul. 2010.
P. M. Asbeck, K. Lee, and J. Min, “Projected performance of heterostructure tunneling FETs in low power microwave and mm-wave applications,” IEEE J. Electron Devices Soc., accepted 2015.
IEDM Tech. Dig., 1998, pp. 789-792.
D. H. Morris, U. E. Avci, and I. A. Young, “Variation-tolerant dense TFET memory with low Vmin matching low-voltage TFET logic,” in Proc. Symp. VLSI Technol. (VLSI Technol.), Jun. 2015, pp. T24–T25. doi: 10.1109/VLSIT.2015.7223688.